This invention relates to a data display circuit which may be used for a display unit of an electronic clock or watch.
In integrating a display circuit which converts display data of an electronic clock or watch into display segment data and displays the same, the integrated circuit design has had to be modified according to the variations in the number of display digits and functions as specified.
FIG. 1 shows a prior art data display circuit used with an electronic clock. The data display circuit of FIG. 1 is provided with a data source 2 composed of a timer circuit or the like which is driven by a timing pulse generator 4 to produce serial time data. The serial time data from the data source 2 are converted into parallel time data by a shift register circuit including four cascade-connected 1-bit shift registers 6 to 9, and then supplied to a decoder circuit 10. The decoder circuit 10, which includes decoders for processing, for example, decimal, duodecimal and scale-of-24 data to process output data from the shift register circuit, converts the output data from the shift register circuit into segment data by digit for each segment in accordance with segment designating signals C1 to C7 and digit designating signals D1 to DN from a control circuit 12. Output data from the decoder circuit 10 are successively supplied to N cascade-connected shift registers 14-1 to 14-N driven by digit enable signals DE which are delivered from the control circuit 12 in synchronism with the digit designating signals D1 to DN. The respective output terminals of these shift registers 14-1 to 14-N are coupled to latches 16-1 to 16-7. The latches 16-1 to 16-7 are controlled, respectively, by output signals of AND gates 18-1 to 18-7 which receive the digit designating signal DN at their respective one input terminals and the segment designating signals C1 to C7 at the other input terminals, respectively. Exclusive OR gates 20-1 to 20-7 which receive respectively the output data of the latches 16-1 to 16-7 modulate the input data into segment energizing signals in accordance with a modulation signal from the control circuit 12, and supply them to display devices 22-1 to 22-7.
In the display circuit as shown in FIG. 1, the decoder circuit 10 decodes the input data from the shift registers 6 to 9 in response to the digit designating signals D1 to DN that are produced while the segment designating signal C1 is being produced, and delivers the decoded data to the shift registers 14-1 to 14-N. When shifting of the output data from the decoder circuit 10 to the shift registers 14-1 to 14-N is completed, the data held in the shift registers 14-1 to 14-N are introduced into the latch circuit 16-1 which is energized by the digit designating signal DN produced at the ending stage of the segment designating signal C1. In consequence, the latch circuit 16-1 may hold first- to Nth-digit data for one of seven segments that are arranged "8"-shaped, for examle. Likewise, during a period when the segment designating signal C2 is produced, first- to Nth-digit data for another segment may be held in the latch circuit 16-2. Thus, first- to Nth-digit segment data for the seven segments are stored respectively in the latch circuits 16-1 to 16-7, and each of the display devices 22-1 to 22-N displays predetermined one of the seven segments, covering from first to Nth digits.
The decoder circuit 10 used with the data display circuit of FIG. 1 includes a number of decoders which are selectively caused to operate by the digit designating signals D1 to DN, the output terminals of the decoders being coupled to a common output terminal through OR circuits. Accordingly, modification of the function of the data display circuit requires substantial modification of the decoder circuit 10 and timing control circuit 12. Further, in order to store the output data of the decoder circuit 10 in the latch circuits 16-1 to 16-7, it is required that the digit designating signals D1 to DN be repeated seven times or be produced for each of the segment designating signals C1 to C7, thereby prolonging the time required.
Thus, this type of data display circuit is unfit for a case where data display need be made on a fine unit of time for stop-watch operation.